Nonvolatile memory device

ABSTRACT

A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of and claims the benefit of priorityfrom U.S. application Ser. No. 12/332,487, filed Dec. 11, 2008, which isbased upon and claims the benefit of priority from Japanese PatentApplication No. 2007-322361 filed in Japan on Dec. 13, 2007. The entirecontents of each of the above-listed applications are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile memory device including anonvolatile memory and a controller unit.

2. Description of Related Art

A NAND flash card is a kind of nonvolatile memory device that enablesrewriting, prevents data erasing when the power is turned off and alsoenables batch erasing. Since NAND flash cards enable downsizing ofcircuits and thus are suitable for providing large capacity, they havebroadly been used as storage devices for digital cameras, portable musicplayers and mobile phones, etc., in recent years.

A NAND flash card includes a NAND flash memory and a controller LSI forthe NAND flash memory (see, for example, Japanese Patent ApplicationLaid-Open Publication No. 2006-48777).

The NAND flash memory includes a logic section, an analog section and amemory cell array, and the controller LSI includes a logic section andan analog section.

Here, in the NAND flash memory and the controller LSI, the respectiveanalog sections generate regulator voltages necessary for the respectivelogic sections, detection signals (reset signals) indicating that anexternally-supplied power supply voltage has reached a minimumguaranteed voltage, and operation clocks, and supply the regulatorvoltages, the detection signal and the operation clocks to therespective logic sections.

Accordingly, the analog section of the NAND flash memory and the analogsection of the controller LSI have configurations that provide similarcircuit functions (e.g., their respective voltage detecting functions),causing problems in that: the circuit sizes are increased; and also ifthere is an error in level of detection of a minimum guaranteed voltagebetween the two voltage detection functions, either the NAND flashmemory or the controller LSI will not operate due to such detectionerror, resulting in the state in which the NAND flash card does notnormally operate.

BRIEF SUMMARY OF THE INVENTION

An aspect of the present invention provides a nonvolatile memory deviceincludes a nonvolatile memory and a controller unit for the nonvolatilememory, wherein: the nonvolatile memory and the controller unit includea first logic section and a second logic section, respectively; thenonvolatile memory includes a voltage detector configured to detect anexternal power supply voltage supplied to both the nonvolatile memoryand the controller unit; and a detection output from the voltagedetector is supplied to the first logic section of the nonvolatilememory provided with the voltage detector, and also to the second logicsection of the controller unit and/or a logic section of at least oneadded nonvolatile memory via a buffer amplifier, simultaneously.

Another aspect of the present invention provides a nonvolatile memorydevice includes a nonvolatile memory and a controller unit for thenonvolatile memory, wherein: the nonvolatile memory and the controllerunit include a first logic section and a second logic section,respectively; the nonvolatile memory includes a regulator configured tosupply a power supply voltage to both of the first and second logicsections of the nonvolatile memory and the controller unit; and thepower supply voltage from the regulator is supplied to the first logicsection of the nonvolatile memory provided with the regulator, and alsoto the second logic section of the controller unit and/or a logicsection of at least one added nonvolatile memory via a buffer amplifier,simultaneously.

Still another aspect of the present invention provides a nonvolatilememory device includes a nonvolatile memory and a controller unit forthe nonvolatile memory, wherein: the nonvolatile memory and thecontroller unit include a first logic section and a second logicsection, respectively; the nonvolatile memory includes an oscillatorconfigured to supply a clock to both of the first and second logicsections of the nonvolatile memory and the controller unit; and theclock from the oscillator is supplied to the first logic section of thenonvolatile memory provided with the oscillator, and also to the secondlogic section of the controller unit and/or a logic section of at leastone added nonvolatile memory via a buffer amplifier, simultaneously.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of a NAND flashcard according to a first embodiment of the present invention;

FIG. 2A is a circuitry diagram illustrating an example configuration ofan output circuit part for a regulator in FIG. 1;

FIG. 2B is a circuitry diagram illustrating an example configuration ofan output circuit part for a voltage detector in FIG. 1;

FIG. 2C is a circuitry diagram illustrating an example configuration ofan output circuit part for an oscillator in FIG. 1;

FIG. 3 is a circuit diagram illustrating an example configuration of aregulator in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a NAND flashcard according to a second embodiment of the present invention;

FIG. 5 is a block diagram illustrating a configuration of a NAND flashcard according to a third embodiment of the present invention;

FIG. 6 is a block diagram illustrating a configuration of a NAND flashcard according to a fourth embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration of a NAND flashcard according to a fifth embodiment of the present invention; and

FIG. 8 is a block diagram illustrating a configuration of a NAND flashcard according to art related to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described with reference tothe drawings.

Prior to describing embodiments of the present invention with referenceto FIGS. 1 to 7, art related to the present invention will be describedwith reference to FIG. 8. For a nonvolatile memory device, a NAND flashcard will be described.

FIG. 8 is a block diagram illustrating a configuration of a NAND flashcard according to art related to the present invention.

As shown in FIG. 8, a NAND flash card 100 includes a NAND flash memory110, and a controller LSI 120, which is a controller unit for the NANDflash memory 110. The NAND flash memory 110 and the controller LSI 120are configured of different chips. Small squares (□) shown in therespective chips indicate input circuit parts including input terminalsand input buffers or output circuit parts including output buffers andoutput terminals for power supply voltages and digital signals. Thecontroller LSI 120 functions as a bridge LSI that provides a bridgebetween a host bus (or a card external terminal) (not shown) throughwhich digital signals are input/output and the NAND flash memory 110that stores the digital signals.

The controller LSI 120 includes a logic section 121 and an analogsection 122.

Here, if the NAND flash card is, e.g., an SD™ card, the logic section121 has a function that converts the SD™ bus specifications, which arethe standards for the input side of the controller LSI 120 to the NANDbus specifications, which are the standards for the output side. Also,the analog section 122 has a function that generates a power supplyvoltage (regulator voltage), a clock signal and a detection signal(reset signal) indicating that a minimum guaranteed voltage has beendetected, which are necessary for operation of the logic section 121,and supplies the power supply voltage, the clock signal and thedetection signal to the logic section 121.

The analog section 122 includes: a regulator 122 a configured to supplya stabilized power supply voltage to the logic section 121; a voltagedetector 122 b configured to detect an external power supply voltage (tobe exact, a minimum guaranteed voltage) supplied from the outside of thecard; an oscillator 122 c configured to supply operation clocks to thelogic section 121; and a reference voltage circuit 122 d configured tosupply a reference voltage to the regulator 122 a and the voltagedetector 122 b. The oscillator 122 c includes a reference oscillator 122c-1 and a frequency multiplier 122 c-2 configured to generate a clocksignal based on a reference oscillation signal from the referenceoscillator 122 c-1.

Meanwhile, the NAND flash memory 110 includes a logic section 111, ananalog section 112 and a memory cell array 113.

Here, the logic section 111 has a function that, when data is written tothe NAND flash memory 110, receives digital signals input according tothe NAND bus specifications, which are the standards for the input sideof the NAND flash memory 110, and writes the data to the memory cellarray 113. Also, the logic section 111 has a function that, when data isread from the NAND flash memory 110, reads the data from the memory cellarray 113, converts the read data into digital signals according to theNAND bus specifications and outputs the digital signals. The analogsection 112 has a function that generates a power supply voltage(regulator voltage), a clock signal, and a detection signal (resetsignal) indicating that a minimum guaranteed voltage has been detected,which are necessary for operation of the logic section 111, and suppliesthe power supply voltage, the clock signal and the detection signal tothe logic section 111.

The analog section 112, as with the analog section 122 of the controllerLSI 120, includes: a regulator 112 a configured to supply a stabilizedpower supply voltage to the logic section 111 and the memory cell array113; a voltage detector 112 b configured to detect an external powersupply voltage (to be exact, a minimum guaranteed voltage) supplied fromthe outside of the card; an oscillator 112 c configured to supply clocksto the logic section 111 and the memory cell array 113; and a referencevoltage circuit 112 d configured to supply a reference voltage to theregulator 112 a and the voltage detector 112 b. The oscillator 112 cincludes a reference oscillator 112 c-1, and a frequency multiplier 112c-2 configured to generate a clock signal based on a referenceoscillation signal from the reference oscillator 112 c-1.

The analog section 122 of the controller LSI 120 are provided with atleast (a) a voltage detector 122 b configured to detect an externalpower supply voltage supplied from the outside of the card, (b) anoscillator 122 c configured to supply clocks to the logic section 121,and (c) a regulator 122 a configured to supply a power supply voltage tothe logic section 121, and the analog section 112 of the NAND flashmemory 110 also a configuration substantially similar to theconfiguration of the analog section 122 of the controller LSI 120.Existence of the two similar analog sections in the NAND flash memory110 and the controller LSI 120 as described above causes the followingproblems:

(1) The analog sections constitute a factor of an increase in footprintand costs; and(2) For the voltage detector 122 b in the controller LSI 120 and thevoltage detector 112 b included in the NAND flash memory 110, either ofproblems a and b below necessarily occurs as a result of an erroroccurring between the voltages detected by the voltage detectors 122 band 112 b, that is,a. A card that can guarantee the minimum guaranteed voltage (V ddmin) ofthe NAND flash memory cannot be manufactured, andb. the NAND flash memory may operate at a voltage lower than the minimumguaranteed voltage of the NAND flash memory.

These problems a and b will be described in details.

For example, where the voltage detector 112 b of the NAND flash memory110 can detect a voltage of no less than 2.7 V, no problem will arise ininput of a same external power supply voltage to both of the voltagedetectors 112 b and 122 b if the voltage detector 122 b of thecontroller LSI 120 can detect a voltage of no less than 2.7 V, too,while a problem will arise if there is a manufacturing error between thedetection functions of the voltage detectors 112 b and 122 b.

In other words, if the NAND flash memory 110 starts operating at avoltage of no less than 2.7 V, it is desirable that the controller LSI120 also starts operating at a voltage of no less than 2.7 V, but eventhough an effort is made to start the operation of both the NAND flashmemory 110 and the controller LSI 120 at a voltage of no less than 2.7V, an error attributable to manufacture necessarily occurs between thevoltages detected by the voltage detectors 112 b and 122 b. Assumingthat the voltage detector 122 b of the controller LSI 120 performs adetection operation at a voltage of no less than 2.5 V and the voltagedetector 112 b of the NAND flash memory 110 performs a detectionoperation at a voltage of no less than 2.7 V due to an error, a problemwill arise when an external power supply voltage, which is inputexternally, is 2.6 V. When the external power supply voltage is 2.6, thecontroller LSI 120 starts operating as a result of determining thevoltage to be of a sufficient level, but the NAND flash memory 110 doesnot operate with 2.6 V as a result of determining the voltage not toreach the minimum guaranteed voltage of 2.7 V (i.e., be outside of theguaranteed minimum range). In other words, with the external powersupply voltage of 2.6 V, the controller LSI 120 enters an operable statewhile the NAND flash memory 110 cannot start operating yet. This problemis one corresponding to problem b above.

Meanwhile, contrary to the above, where the controller LSI 120 canoperate at a voltage of no less than 2.8 V and the NAND flash memory 110can operate at 2.7 V, when the external power supply voltage reaches 2.7V, the NAND flash memory 110 can operate, while the controller LSI 120cannot operate unless the voltage is further increased to 2.8 V, whichrequires the outside to provide a large external power supply voltage,resulting in deterioration of the performance of the NAND flash card.This problem corresponds to problem a above.

In summary, where the card has a configuration in which two voltagedetectors 112 b and 122 b are combined, either of problems a and b abovewill occur as a result of an detection error between the voltagedetectors.

Hereinafter, embodiments of the present invention will be described.

First Embodiment

FIGS. 1 to 3 relate to a first embodiment of a nonvolatile memory deviceaccording to the present invention: FIG. 1 is a block diagramillustrating a configuration of a NAND flash card 100A according to thefirst embodiment; FIGS. 2A to 2C show example configurations of outputcircuit parts T1 to T3 in FIG. 1; and FIG. 3 shows an exampleconfiguration of a regulator 112 a in FIG. 1. The NAND flash card maybe, e.g., an SD™ card, a SmartMedia (registered trademark) card, aCompactFlash (registered trademark) or a USB memory card. Here,description will be given in terms of an SD™ card as the NAND flashcard.

In the configuration in FIG. 1, the entire analog section 122 in thecontroller LSI 120 in FIG. 8 has been removed. Accordingly, FIG. 1 showsa configuration in which an analog section 112 in a NAND flash memory110A doubles as an analog section in a controller LSI 120A. The NANDflash memory 110A and the controller LSI 120A are configured ofdifferent chips, and each chip is provided on a wiring pattern of aprinted wiring substrate. Small squares (□) shown in each chip indicateinput circuit parts including input terminals and input buffers oroutput circuit parts including output buffers and output terminals forpower supply voltages and digital signals. Here, “buffer” means “bufferamplifier”.

More specifically, the controller LSI 120A in FIG. 1 includes a logicsection 121 only, and the controller LSI 120A is provided with threeinput circuit parts t1, t2 and t3 configured to load a regulator voltagefrom a regulator 112 a on the NAND flash memory 110A side, a resetsignal, which is a detection output from a voltage detector 112 b, and aclock signal from an oscillator 112 c into the logic section 121. Eachof the input circuit parts t1, t2 and t3 includes an input terminal andan input buffer.

Meanwhile, the NAND flash memory 110A has a configuration in which theNAND flash memory 110 in FIG. 8 is provided with three output circuitparts T1, T2 and T3. In other words, the NAND flash memory 110A areprovided with three output circuit parts T1, T2 and T3 configured tooutput a regulator voltage from the regulator 112 a, a reset signal,which is a detection output from the voltage detector 112 b, and a clocksignal from the oscillator 112 c to the outside, respectively. Each ofthe output circuit parts T1, T2 and T3 includes an output buffer and anoutput terminal. A logic section 111, an analog section 112 and a memorycell array 113 in the NAND flash memory 110A are similar to those inFIG. 8.

In FIG. 1, a host bus includes a card external terminal part (omitted inthe Figure) of the NAND flash card 100A externally connected to anexternal host device (not shown). A digital signal of 3.3 V at a highlevel and 0 V at a low level is input to the card external terminal partof the NAND flash card 100A and supplied to the logic section 121 of thecontroller LSI 120A.

The logic section 121 of the controller LSI 120A has a function thatdetects whether a signal input from the host bus is at a high level or alow level, and also has a function that converts the SD™ busspecifications, which are the standards for the input side of thecontroller LSI 120A, to the NAND bus specifications on the output side,which are the standards for the output side.

Meanwhile, the logic section 111 of the NAND flash memory 110A has afunction that, when data is written to the NAND flash memory 110,receives digital signals input according to the NAND bus specifications,which are the standards for the input side of the NAND flash memory110A, and writes the data to the memory cell array 113. The logicsection 111 also has a function that, when data is read from the NANDflash memory 110A, reads the data from the memory cell array 113,converts the read data into digital signals according to the NAND busspecifications and outputs the digital signals.

The voltage detector 112 b has a function that determines (detects)whether or not a minimum guaranteed voltage (e.g., 2.7 V) necessary forthe specifications of an SD™ card is input as an external power supplyvoltage, and supplies a signal of the detection to the logic section 111and also to the logic section 121, as a reset signal.

The regulator 112 a receives an input of an external power supplyvoltage of 3.3 V, generates a stabilized voltage of 1.5 V using areference voltage from a reference voltage circuit 112 d, and suppliesthe stabilized voltage to the logic sections 111 and 121. Although theinsides of the logic sections 111 and 121 operate at 1.5 V as a powersupply voltage, unless the voltage detector 112 b detects that theminimum guaranteed voltage (2.7 V) is secured, the logic sections 111and 121 are not reset, and thus the logic sections 111 and 121 do notstart operating.

For the start of operation of the logic sections 111 and 121, even ifwhether an input signal from the host bus is at a high level or a lowlevel is normally detected in the logic sections 111 and 121, the inputsignal is not employed as a digital signal of a high level/low levelfrom the host bus in the logic sections 111 and 121 unless the voltagedetector 112 b detects a voltage equal to or exceeding the minimumguaranteed voltage (2.7 V).

While in the configuration shown in FIG. 1 (and the configurations shownin FIGS. 4 to 7), for a power supply voltage for the oscillator 112 c(and an oscillator 122 c), a regulator voltage from the regulator 112 ais used, the external power supply voltage may be used as the powersupply voltage for the oscillator 112 c.

With the above-described configuration, a regulator voltage generated inthe regulator 112 a in the analog section 112 of the NAND flash memory110A, a detection signal (reset signal) indicating the detection of aminimum guaranteed voltage, which is output from the voltage detector112 b, and a clock signal generated in the oscillator 112 c are suppliedto the logic sections 111 and 121 simultaneously, and accordingly,problems, such as operation failure, due to an error between twovoltages detected by the voltage detector in the controller LSI and thevoltage detector included in the NAND flash memory, which occur in theconfiguration of the related art in FIG. 8, will not occur.

In the configuration shown in FIG. 1, in the chip of the NAND flashmemory 110A, the analog section 112 is built on a same semiconductorsubstrate (wafer) together with the logic section 111 and the memorycell array 113. With this configuration, the logic section 111 and thememory cell array 113 in NAND flash memory 110A, especially the memorycell array 113, require voltages, such as a bias voltage for drivingmemory cells to perform writing/reading, to be set (controlled) with ahigh degree of accuracy. Thus, the analog section 112, which supplies aregulator voltage and a clock signal to the memory cell array 113,requires a high degree of accuracy as the memory cell array 113 and thelogic section 111 do.

Meanwhile, the logic section 121 in the chip of the controller LSI 120Amainly functions to convert the SD™ bus specifications to the NAND busspecifications, and thus does not require setting, e.g., a voltage witha high degree of accuracy, which is necessary for controlling the memorycell array 113. Accordingly, if an analog section 112 is provided in thechip of the controller LSI 120A, the analog section 112 would notrequire a high degree of accuracy either. In other words, while the chipof the NAND flash memory 110A is required to be manufactured with a highdegree of accuracy, the chip of the controller LSI 120A is less requiredto be manufactured with a high degree of accuracy compared to the NANDflash memory 110A.

Accordingly, when the configuration of the NAND flash card of therelated art in FIG. 8 is changed to include only one analog section, itis preferable to employ the configuration shown in FIG. 1, which usesthe analog section 112 of the NAND flash memory 110A also as an analogsection of the controller LSI 120A. The reason is that sincemounted-circuit portions of the NAND flash memory 110A (i.e., the memorycell array 113 and the logic section 111) essentially require a highdegree of accuracy, use of the analog section 112 on the NAND flashmemory 110A side, which is required to be manufactured with a highdegree of accuracy corresponding to these mounted-circuit portionsenables supply of a regulator voltage, a rest signal and a clock signalwith a necessary degree of accuracy or higher from the analog section112 to the controller LSI 120A, and consequently enables supply of aregulator voltage, a reset signal and a clock signal with a necessarydegree of accuracy or higher to both the NAND flash memory 110A and thecontroller LSI 120A.

FIGS. 2A, 2B and 2C show example configurations of the output circuitparts T1, T2 and T3, respectively.

Each of the output circuit parts T1, T2 and T3 includes an output bufferas an impedance conversion element that performs impedance conversion sothat the effect of the outside of the NAND flash memory 110A does notreach the internal circuits, and an output terminal. FIG. 2A shows theoutput circuit part T1 including a voltage follower T1-1 as an impedanceconversion element that guides a regulator output of the regulator 112 ato an output terminal T1-2, and the output terminal T1-2. FIG. 2B showsthe output circuit part T2 including a serial circuit T2-1 of twoinverters as an impedance conversion element that guides a detectionoutput (reset signal) of the voltage detector 112 b to an outputterminal T2-2, and the output terminal T2-2. FIG. 2C shows the outputcircuit part T3 including a serial circuit T3-1 of two inverters as animpedance conversion element that guides a clock output of theoscillator 112 c to an output terminal T3-2, and the output terminalT3-2. When a reference voltage from the reference voltage circuit 112 d(or 122 d) is output to the outside, the configuration of the voltagefollower in FIG. 2A may be used.

Each of the input circuit parts t1, t2 and t3 includes an inputterminal, and an input buffer as an impedance conversion element thatperforms impedance conversion so that the effect of the outside does notreach the internal circuits. The input buffers in this case haveconfigurations similar to those of the output buffers shown in FIGS. 2Ato 2C.

FIG. 3 shows an example configuration of the regulator 112 a.

An external power supply voltage of, e.g., 3.3 V is supplied to a drain(D) of a junction-type FET Q1. A serial circuit of a resistance R1 and aresistance R2 is connected between a source (S) of the FET Q1 and areference potential point, a voltage at the point of the serialconnection is input to a positive input terminal of an operationalamplifier OP1, and a reference voltage of 1.0 V from the referencevoltage circuit 112 d is input to a negative input terminal of theoperational amplifier OP1. For the reference voltage circuit 112 d,e,g., a constant voltage diode is used, and even though a direct currentpower supply E varies between 1.2 to 4.0 V, a reference voltage of 1.0 Vcan constantly be generated.

When the FET Q1 is turned off when a voltage input to a gate (G) of theFET Q1 is a predetermined negative voltage lower than 0 V (e.g., −1.5V), and a voltage larger than the predetermined voltage is supplied tothe gate of the FET Q1, a current between the source and the drain isincreased (e.g., the conduction resistance is lowered), enabling avoltage output to the source when a difference in voltage between thegate and the source is 0 V to be stabilized at 1.5 V. The regulatorvoltage of 1.5V, as described above, is used as a power supply voltagefor the logic sections 111 and 121 (also for the memory cell array 113and the oscillator 112 c).

According to the present embodiment, the analog section of thecontroller LSI can be removed, saving the area of the analog section aswell as providing the advantage of cost reduction. Also, a reset signalis supplied only from the voltage detector on the NAND flash memory sideto the logic section of the controller LSI, and accordingly, problems,such as operation failure, due to an error between two voltages detectedby the voltage detector in the controller LSI and the voltage detectorincluded in the NAND flash memory, which occurs in the configurationshown in FIG. 8, do not occur. Furthermore, a regulator voltage, a restsignal and a clock signal with a high degree of accuracy can be suppliedto both the NAND flash memory and the controller LSI.

Second Embodiment

FIG. 4 is a block diagram illustrating a configuration of a NAND flashcard 100B according to a second embodiment of the present invention.

In the first embodiment shown in FIG. 1, a configuration in which theNAND flash memory 110A supplies a regulator voltage, a reset signal anda clock signal to the controller LSI 120A has been described.

In the second embodiment shown in FIG. 4, the analog section of thecontroller LSI 120 in FIG. 8 has partially been removed. In other words,the second embodiment is configured so that: the reference voltagecircuit 122 d, the voltage detector 122 b and the reference oscillator122 c-1 are removed from the analog section 122 of the controller LSI120 in the NAND flash card 100 in FIG. 8, while the regulator 122 a andthe frequency multiplier 122 c-2 are retained; and a regulator voltage,a reset signal and a clock signal necessary for the logic section 121 ofthe controller LSI 120 are obtained from the regulator 122 a and thefrequency multiplier 122 c-2, which are retained in the controller LSI120, and the reference voltage circuit 112 d, the voltage detector 112 band the reference oscillator 112 c-1 in the analog section 112 of theNAND flash memory 110.

Unlike the configuration in FIG. 1, a reference voltage of a referencevoltage circuit 112 d in the NAND flash card 100B is output to theoutside via an output circuit part T1, and then supplied to a regulator122 a of a controller LSI 120B via an input circuit part t1. Theregulator 122 a generates a regulator voltage using an external powersupply voltage and a reference voltage from the input circuit part t1,and supplies the regulator voltage to a logic section 121. Also,reference clocks from a reference oscillator 112 c-1 in an oscillator112 c in the NAND flash card 100B are output to the outside via anoutput circuit part T-3, and then supplied to a frequency multiplier 122c-2 in the controller LSI 120B via an input circuit part t3. Thefrequency multiplier 122 c-2 generates a clock signal by multiplying thefrequency of the reference clocks and supplies the clock signal to thelogic section 121. Also, a detection output (reset signal) from avoltage detector 112 b in the NAND flash card 100B is supplied to thelogic section 121 of the controller LSI 120B via an output circuit partT2 and an input circuit part t2.

The above configuration is different from the first embodiment in FIG. 1in that: the analog section of the controller LSI 120B has partiallybeen removed and an analog section 112′ of a NAND flash memory 110Cdoubles as the removed portion of the analog section of the controllerLSI 120B. The NAND flash memory 110C and the controller LSI 120B areconfigured of different chips, and each chip is provided on a wiringpattern on a printed wiring substrate.

Advantages of the configuration in FIG. 4 over the configuration in FIG.1 will be described. In the case of the configuration in FIG. 1, it isnecessary to obtain a high-frequency clock signal (frequency multiplieroutput) necessary for the chip of the controller LSI from the chip ofthe NAND flash memory. Then, the part of connection between the NANDflash memory 110C and the controller LSI 120B is on the printed wiringsubstrate where a large capacity is provided, increasing the currentconsumption.

Meanwhile, in the case of the configuration in FIG. 4, since thefrequency multiplier 122 c-2 is retained in the controller LSI 120B, thefrequency of a signal received by the controller LSI 120B from the NANDflash memory 110C is a substantially-low frequency from the referenceoscillator (which is substantially lower compared to the multipliedfrequency from the frequency multiplier), and since the frequency of asignal transmitted in the wiring pattern on the printed wiring substrateis low being the frequency of the reference oscillator, a substantiallysmaller amount of current is consumed in that portion compared to thecase of use of the multiplied frequency. Also, there is an advantage ofthe frequency multiplier 122 c-2 exiting in the controller LSI 120B inthat the frequency of a clock signal can be changed between thecontroller LSI 120B and the NAND flash memory 110C separately. In otherwords, by means of changing a multiple for the frequency multiplier 112c-2 of the NAND flash memory 110C and a multiple for the frequencymultiplier 122 c-2 of the controller LSI 120B, the frequency of a clocksignal on the NAND flash memory 110C side and the frequency of a clocksignal on the controller LSI 120B side can be changed separately.

Furthermore, since the regulator 122 a is retained in the controller LSI120B, the regulator voltage in the logic section 121 can easily bechanged variously (e.g., the regulator voltage can easily be changed toa low voltage aiming at current consumption) as needed. In other words,the voltage of the regulator on the controller LSI 120B side can beadjusted. It should be understood that the regulator voltage of a logicsection 111 of the NAND flash memory 110C can also be adjustedseparately, and thus, voltages can separately be set in the regulator122 a in the controller LSI 120B and the regulator 122 a in the NANDflash memory 110C. In the configuration in FIG. 4, compared to therelated art in FIG. 8, the NAND flash memory 110C includes a referenceoscillator and a reference voltage circuit, and only reference clocksand a reference voltage are supplied to the frequency multiplier 122 c-2and the regulator 122 a in the controller LSI 120B, respectively,providing an advantage in that it is sufficient to provide one referenceoscillator and one reference voltage circuit, which are difficult toprovide in terms of design.

According to the present embodiment, the analog section of thecontroller LSI can partially be removed, reducing the area of the analogsection and providing the advantage of cost reduction. Also, a resetsignal is supplied from the voltage detector on the NAND flash memoryside to the controller LSI in common with the logic section of the NANDflash memory, and thus, problems, such as operation failure, due to anerror between voltages detected by the voltage detector in thecontroller LSI and the voltage detector included in the NAND flashmemory, which occurs in the configuration in FIG. 8, do not occur.Furthermore, as described above, different clock signal frequencies andregulator voltages can be set between the NAND flash memory and thecontroller LSI. Also, the current consumption can be reduced byconveying a low signal frequency of clocks from the reference oscillatoron the NAND flash memory side to the controller LSI side.

Third Embodiment

FIG. 5 is a block diagram illustrating a configuration of a NAND flashcard 100C according to a third embodiment of the present invention.

The third embodiment shown in FIG. 5 is configured so that when a NANDflash card including a plurality of NAND flash memories is provided, aregulator voltage, a reset signal and a clock signal are output from oneNAND flash memory, and supplied also to the other NAND flash memories.

The third embodiment shown in FIG. 5 has a configuration in which one ormore NAND flash memories 110B (one NAND flash memory in the Figure) eachincluding a logic section and a memory cell array, which is obtained byremoving the analog section from the NAND flash card 100A shown in FIG.1, is added. A plurality of NAND flash memories 110B may be added to aNAND flash card 100A in parallel. Where one or more NAND flash memories110B are connected to the NAND flash card 100A in parallel, outputcircuit parts T1′, T2′, T3′ and T4′ and input circuit parts t1′, t2′,t3′ and t4′ are provided to lines for a regulator voltage, a clocksignal, a reset signal and a reference voltage. As a result of addingone or more NAND flash memories 110B as described above, a NAND flashcard with a large capacity can be provided.

Data according to the NAND bus specifications output from a logicsection 121 of a controller LSI 120A is supplied to a logic section 111of a first NAND flash memory 110A, and can also be supplied to a logicsection 111′ of a second NAND flash memory 110B. Also, chip enablesignals CE0 and CE1 can be output from the controller LSI 120A, thefirst NAND flash memory 110A can be selected by the chip enable signalCE0, and the second NAND flash memory 110B can be selected by the chipenable signal CE1. Normally, the first NAND flash memory 110A isselected, and when the storage capacity of the memory cell array in thefirst NAND flash memory 110A has been filled, the second NAND flashmemory 110B is selected and thereby storing can be continued.

More specifically, by means of one logic section 121 included in thecontroller LSI 120A, a plurality of logic section-memory cell arraypairs, each pair including a logic section 111 and a memory cell array113, can selectively be controlled to operate, and by means of oneanalog section 112 included in the NAND flash memory 110A, a regulatorvoltage, a reset signal, a clock signal and a reference voltagenecessary for the plurality of logic section-memory cell array pairs,each pair including a logic section 111 and a memory cell array 113, canbe supplied.

According to the present embodiment, a regulator voltage, a reset signaland a clock signal generated in one NAND flash memory can be suppliedalso to the one or more other NAND flash memories with no analogsections, and thus even thought the storage capacity of one NAND flashmemory has been filled with data, the used flash memory can be switchedto another NAND flash memory connected in parallel to store data.Consequently, analog sections can be reduced and the storage capacitycan be increased.

Fourth Embodiment

FIG. 6 is a block diagram illustrating a configuration of a NAND flashcard 100D according to a fourth embodiment of the present invention.

The fourth embodiment shown in FIG. 6 is configured so that when a NANDflash card including a plurality of NAND flash memories is provided, areference voltage, a reset signal and reference clocks are output fromone NAND flash memory 110C and supplied also to the other NAND flashmemories 110D.

The fourth embodiment shown in FIG. 6 has a configuration in which oneor more NAND flash memories 110D (one NAND flash memory 110D in theFigure) each including a logic section 111′, a memory cell array 113′,and a regulator 112 a′ and a frequency multiplier 112 c′ as an analogsection are added to the NAND flash card 100B shown in FIG. 4. Aplurality of NAND flash memories 110D may be added to the NAND flashcard 100B (see FIG. 4) in parallel. When one or more NAND flash memories110D are connected to the NAND flash card 100B in parallel, outputcircuit parts T1″, T2″ and T3″ and input circuit parts t1″, t2″ and t3″are provided to lines for a reference voltage, a reset signal andreference clocks. As a result of adding one or more NAND flash memories110D, a NAND flash card with a large capacity can be provided. Anexternal power supply voltage is supplied to the regulators 112 a′ inthe NAND flash memories 110D via, e.g., a controller LSI 120B, the NANDflash memory 110C and external wirings.

Data according to the NAND bus specifications output from a logicsection 121 of the controller LSI 120B is supplied to a logic section111 of a first NAND flash memory 110C, and can also be supplied to alogic section 111′ of a second NAND flash memory 110D. Furthermore, chipenable signals CE0 and CE1 can be output from the controller LSI 120B,the first NAND flash memory 110C can be selected by the chip enablesignal CE0, and the second NAND flash memory 110D can be selected by thechip enable signal CE1. Normally, the first NAND flash memory 110C isselected, and when the storage capacity of the memory cell array of thefirst NAND flash memory 110C has been filled, the second NAND flashmemory 110D is selected and thereby storing can be continued.

More specifically, by means of a logic section 121, a regulator 122 aand a frequency multiplier 122 c-2 included in the controller LSI 120B,a NAND flash memory 110C including a set of a logic section 111, amemory cell array 113 and the analog section 112′, and the NAND flashmemories 110D including one or more sets of a logic section, a memorycell array, a regulator and a frequency multiplier can be selectivelycontrolled to operate, and by means of the analog section 112′ includedin the NAND flash memory 110C, a reference voltage, a rest signal, areference clock and an external power supply voltage necessary for theone or more sets of a logic section, a memory cell array, a regulatorand a frequency multiplier, each set including the logic section 111′,the memory cell array 113′, the regulator 112 a′ and the frequencymultiplier 112 c′, can be supplied.

According to the present embodiment, a configuration in which areference voltage, a reset signal and a reference clock generated in oneNAND flash memory is supplied also to one or more other NAND flashmemories each having only a regulator and a frequency multiplier as ananalog section can be provided, enabling providing a plurality of NANDflash memories in which a regulator voltage and a clock signal can beadjusted by means of the regulator and the frequency multiplier to aNAND flash card. Consequently, even though the storage capacity of oneNAND flash memory has been filled with data, data can be stored byswitching the used flash memory to another NAND flash memory connectedin parallel. As a result, the areas of the analog sections can bereduced and the storage capacity can be increased.

Fifth Embodiment

FIG. 7 is a block diagram illustrating a NAND flash card E according toa fifth embodiment of the present invention.

The fifth embodiment shown in FIG. 7 has a configuration in which theanalog section 112 of the NAND flash memory 110A in the embodiment inFIG. 1 has been taken out of the NAND flash memory 110A and separatedoff as an analog section block 130, which is another chip.

The above-described output circuit parts T1, T2 and T3 and input circuitparts t1, t2 and t3, which are configured to output a necessaryregulator voltage, voltage detector 112 b's detection signal (restsignal) and clock signal from an oscillator 112 c from an analog section112 to a logic section 121, are provided to lines between the analogsection 112 and the logic section 121 of a controller LSI 120A. Also,the output circuit parts T1', T2′ and T3′ and input circuit parts t1′,t2′ and t3′ are provided to lines between the analog section 112 and amemory cell array 113.

Where the above-described configuration is applied to, e.g., the NANDflash memory 110A in the NAND flash card 100C in FIG. 5 including twoNAND flash memories, the NAND flash memory 110A (see FIG. 5) is dividedinto a NAND flash memory 110B (see FIG. 7) and an analog section block130 (see FIG. 7), the configurations of two NAND flash memories 110A and110B in FIG. 5 are all made to be a simple configuration that onlyincludes a logic section and a memory cell array, providing an advantagein facilitating circuit design and circuit chip manufacture. In otherwords, in FIG. 5, the NAND flash card 100C can be configured of acontroller LSI 120A, an analog section block 130, two NAND flashmemories 110B having no analog sections. Similarly, when a NAND flashcard including N (N is an integer no less than two) NAND flash memoriesis configured, such NAND flash card can be configured by a controllerLSI 120A, an analog section block 130 and N NAND flash memories 110Bhaving no analog sections, facilitating circuit design and circuit chipmanufacture.

The present invention is limited neither to NAND flash cards, nor to SD™cards, and can broadly be applied to nonvolatile memory devicesincluding a storage portion and a control portion.

As described above, the present invention enables downsizing of circuitsas a result of reducing analog sections, and also enables provision of anonvolatile memory device that does not cause problems such as operationfailure due to an error between two voltages detected by a voltagedetector used in a controller unit and a voltage detector included in anonvolatile memory. The present invention further enables elimination ofnot only a detection error between a voltage detector in a nonvolatilememory and a voltage detector in a controller unit for the nonvolatilememory, but also an error between regulator voltages and an errorbetween operation clocks. Furthermore, the present invention enablesreduction of current consumption, an increase in storage capacity, andfacilitation of circuit design and circuit chip manufacture.

Having described the embodiments of the invention referring to theaccompanying drawings, it should be understood that the presentinvention is not limited to those precise embodiments and variouschanges and modifications thereof could be made by one skilled in theart without departing from the spirit or scope of the invention asdefined in the appended claims.

1. A nonvolatile memory device comprising a nonvolatile memory and a controller unit for the nonvolatile memory, wherein: the nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively; the nonvolatile memory includes a regulator configured to supply a power supply voltage to both of the first and second logic sections of the nonvolatile memory and the controller unit; and the power supply voltage from the regulator is supplied to the first logic section of the nonvolatile memory provided with the regulator, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.
 2. A nonvolatile memory device comprising a nonvolatile memory and a controller unit for the nonvolatile memory, wherein: the nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively; the nonvolatile memory includes an oscillator configured to supply a clock to both of the first and second logic sections of the nonvolatile memory and the controller unit; and the clock from the oscillator is supplied to the first logic section of the nonvolatile memory provided with the oscillator, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously.
 3. The nonvolatile memory device according to claim 1, wherein: the nonvolatile memory includes a reference voltage circuit configured to generate a reference voltage; and the reference voltage from the reference voltage circuit is supplied to a first regulator in the nonvolatile memory provided with the reference voltage circuit, and also to a second regulator provided in the controller unit and/or a regulator of at least one added nonvolatile memory via a buffer amplifier.
 4. The nonvolatile memory device according to claim 2, wherein: the nonvolatile memory includes a reference oscillator configured to generate a reference clock; and the reference clock from the reference oscillator is supplied to a first frequency multiplier in the nonvolatile memory provided with the reference oscillator, and also to a second frequency multiplier provided in the controller unit and/or a frequency multiplier of at least one added nonvolatile memory via a buffer amplifier.
 5. The nonvolatile memory device according to claim 3, wherein regulator voltages output from the first and second regulators and the regulator of the at least one added are set to mutually different voltages.
 6. The nonvolatile memory device according to claim 4, wherein frequencies of clock signals output from the first and second frequency multipliers and the frequency multiplier of the at least one added nonvolatile memory are set to mutually different frequencies.
 7. The nonvolatile memory device according to claim 1, wherein the first and second logic sections can operate using a predetermined stabilized voltage from the regulator as a power supply voltage, while unless the voltage detector detects that a predetermined minimum guaranteed voltage, which is higher than the stabilized voltage, is secured, the first and second logic sections are not reset, and the first and second logic sections do not start operating.
 8. The nonvolatile memory device according to claim 7, wherein for start of operation of the first and second logic sections, even if whether an input signal from a host bus is at a high level or a low level is normally detected in the first and second logic sections, the input signal is not employed as a digital signal of a high level/low level from the host bus in the first and second logic sections unless the voltage detector detects a voltage equal to or exceeding the predetermined minimum guaranteed voltage. 